The present invention relates to programmable logic devices generally and, more particularly, to a clocking scheme for a programmable logic device architecture.
Traditionally there are two types of programmable logic architectures: complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). The CPLD can be constructed as a one-dimensional array of logic blocks made of 16 macrocells and a product term array connected through a single central interconnect scheme. The CPLD achieves high performance by being able to complete a complex logic function in a single pass of the logic array and has predictable timing by connecting every output or I/O pin to every logic block input through the central interconnect structure. The CPLD can be non-volatile by using an EEPROM process.
However, the architecture of the conventional CPLD has disadvantages. A complex process technology limits performance and increases cost. A high standby power limits capacity and applications. The conventional CPLD has no available on-chip RAM. The maximum capacity of the conventional CPLD is limited by interconnect structure performance, power, technology and die cost. The core voltages, I/O voltages, and I/O standards of the conventional CPLD are not flexible. The I/O cells need a synchronous output enable (OE) to support a synchronous circuit architecture with minimal bus latency (e.g., as found in NoBL(trademark) SRAMs manufactured by Cypress Semiconductor Corp. or ZBT(trademark) devices manufactured by Integrated Device Technology) memory.
An FPGA architecture is constructed from a two dimensional array of logic blocks called CLBs. The CLBs are made from 4-input look-up-tables (LUTs) and flip-flops. The LUTs can be used as distributed memory blocks. The CLBs are connected by a segmented interconnect structure. The FPGA architecture supports a low standby power and the LUTs can use a simple logic CMOS process. Since the two-dimensional array of CLBs and the segmented interconnect structure are scalable, the FPGA architecture can achieve high densities.
However, the architecture of the FPGA has disadvantages. A volatile process requires a FLASH/EEPROM to be added to the design. The segmented routing architecture limits performance and makes timing unpredictable. Implementing a dual port or FIFO memory with LUTs is slow and inefficient. A complex xe2x80x9cdesign-in-processxe2x80x9d is required because the conventional FPGAs do not have predictable timing, short compile times, in-system-reprogrammability (e.g., ISR(copyright), a registered Trademark of Cypress Semiconductor Corp.) or pin fixing. The core voltage of the conventional FPGA is (i) not flexible and (ii) driven by the current process. The conventional FPGA makes product migration very difficult and does not support full JTAG boundary scan and configuration.
Programmable logic designs generally use phased lock loops for one of two reasons: (i) to time division multiplex circuits implemented in the programmable logic device to get a higher performance with fewer device resources; or (ii) to take advantage of the positioning of the internally generated clock edges to shift performance towards improved setup, hold or clock-to-out times.
The present invention concerns a programmable logic device comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first plurality of clock signals in response to (i) one or more input clock signals and (ii) a configuration signal. The second circuit may be configured to generate a second plurality of clock signals in response to (i) said first plurality of clock signals and (ii) said configuration signal. The third circuit may be configured to present a third plurality of clock signals selected from (i) said one or more input clock signals, (ii) said second plurality of clock signals in response to said configuration signal.
The objects, features and advantages of the present invention include providing a clocking scheme for a programmable logic device that may: (i) be spread spectrum aware; (ii) provide a lock detect signal that can be sent off-chip via an I/O pin; (iii) provide global clock signals to off-chip devices; (iv) provide de-skewing options; (v) provide a plurality of clock phases and/or (vi) support a JTAG boundary scan (including INTEST) for easy debugging.